| 摘要 |
A method is provided that includes a step for setting a maximum number of concurrently allocated queue entries to service writeback evictions. The method also includes a step of setting a register bit based on cache requests. The method also includes a step for dynamically selecting, based on the register bit set, one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated in in any free entry based on priority. According to another embodiment of the invention, a computer system is provided that includes at least one computer processor. The computer processor provided has at least one cache memory and a cache controller. Further included is a register coupled to the computer processor. Also, a memory bus is provided that is coupled to the computer processor. A memory is included that is coupled to the memory bus. A controller for dynamically selecting between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority is also included. The controller for dynamically selecting between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority includes a register bit within the register that is capable of being set and cleared. The computer processor queries the register to determine if the register bit is either set and cleared.
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