Delay locked loop with reduced noise response

摘要

A delay locked loop is disclosed which is less responsive to noise so as to improve an AC parameter tAC. The delay locked loop generally includes: a phase detector, a shift register, and a noise determining circuit which is enabled when the delay locked loop is locked for controlling driving of the shift register by determining whether a phase comparison signal from the phase detector is produced by noise. The noise determining circuit drives the shift register when the phase comparison signal has information for driving the shift register at least three times sequentially.