| 摘要 |
A clock synchronization semiconductor memory device in which the pre-charging time tRP can be accelerated by the variable delay time for write recovery. There is provided a unit for checking whether or not at least one clock cycle before the inputting of the pre-charge command is that for the write operation, and for holding the checked result. There is also provided a unit for performing switching control at the time of inputting the pre-charge command, responsive to the checked result, as to whether or not a pre-set delay time is to be introduced as from the time of inputting the pre-charge command until word line resetting.
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