SEMICONDUCTOR MEMORY WITH PROGRAMMABLE BITLINE MULTIPLEXERS

摘要

There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.