| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory having a redundant circuit in which the circuit scale of a redundant circuit and the chip size are reduced. SOLUTION: This memory has a plurality of memory regions, and redundant memory region, redundant address regions, and redundant flag regions corresponding to these memory regions respectively. The redundant address region holds a second address indicating a defective memory cell as address information. The redundant flag region holds relieving information indicating that the redundant memory region is used. In operation of the memory cell, a defective memory cell is not selected in accordance with address information. The redundant memory cell relieving a defective memory cell is selected in accordance with relieving information. Since address information is not used for selecting a redundant memory cell, a time required for selecting a redundant memory cell after selection of a word line can be shortened, delay of access time can be prevented in relieving a memory cell.</p> |
