| 摘要 |
PROBLEM TO BE SOLVED: To dispense with a parallel/serial conversion circuit, a delay unit with 1,497 stages and a serial/parallel conversion circuit in an error and synchronism detection circuit. SOLUTION: Byte date in units of seven bits are rearranged into byte data, where one byte is constituted of eight bits by a data-rearranging block 1. Byte data in the unit of eight bits are used consistently, and byte data are stored in a data storage block 3 constituted of RAM. A parity check block 2 receives byte data from the data rearranging block 1 and byte data delayed by 1496 from the data storage block 3 and performs synchronism detection operation and the parity check operation of byte data. Thus, the parallel-serial conversion circuit and the serial-parallel conversion circuit are replaced by a byte/byte conversion processing. Since byte date are stored by using RAM, the delay unit of 1496 stages is dispensed with. |
