MULTIPLE PORTS MEMORY-CELL STRUCTURE

摘要

A semiconductor memory array includes a memory cell read/write voltage control circuit for controlling each of the first [BL1] and a second [BL1#] bit lines to have a bit line voltage higher, lower and a medium voltage range between a first voltage [V0] and a second voltage [V1] wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port independently carrying out a read/write operation by activating the first [WL1] and second [WL1#] word lines respectively and by controlling the first and second word lines respectively to have a bit line voltage higher, lower or within the medium range between the first and second voltage.