发明名称 Method and system for improving clock speed for data and function opcodes between two different clock speeds
摘要 A method and system is provided for synchronizing data between an application layer having a first clock speed and a circuit having a second clock speed. The first clock speed generally being faster than the second clock speed. The second clock speed typically being determined by an appropriate standard. Data and a function opcode representative of a computation to be performed on at least a portion of the data, is received at a synchronizing element from the application layer. The synchronizing element may be a first in first out type device. The data and its associated function opcodes are stored by the synchronizing element until transmitted to a circuit in accordance with the second clock speed. A compute logic in the circuit performs a computation on at least a portion of the data based on the associated function opcode. A system is also provided for synchronizing data between an application layer and a logic circuit. The system may be advantageously employed in audio/visual applications.
申请公布号 US2002099968(A1) 申请公布日期 2002.07.25
申请号 US20010769847 申请日期 2001.01.25
申请人 BOMMAJI ANURADHA 发明人 BOMMAJI ANURADHA
分类号 G06F9/38;H04N7/62;(IPC1-7):G06F1/04;G06F1/12;G06F5/06 主分类号 G06F9/38
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