| 摘要 |
A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines. A plurality of spacers are formed on sidewalls of the bit line stacked structure. A plurality of second conductive layers are formed conformal to the surfaces of the trenches. The second conductive layers are patterned to form a plurality of bottom electrodes electrically connected to the node contacts.
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