| 摘要 |
Structures and methods for programmable logic arrays are provided with logic cells, or floating gate transistors, which can operate with lower applied control gate voltages than conventional programmable logic arrays. The programmable logic arrays of the present invention do not increase the costs or complexity of the fabrication process. According to the teachings of the present invention, the floating gate capacitance in the logic cells is much smaller than the control gate capacitance such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide. The programmable logic arrays include a plurality of input lines for receiving an input signal and a plurality of output lines. One or more arrays is provided which includes a first logic plane and a second logic plane connected between the input lines and the output lines. The first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal. Each logic cell includes a source and a drain region in a horizontal substrate with a channel region therebetween. A first vertical gate is located above a portion of the channel region and separated from the channel region by a first oxide thickness. A second vertical gate is located above another portion of the channel region and separated therefrom by a second oxide thickness.
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