| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a memory control unit, an information processing unit, a memory control method, and a storage medium which can surely transmit a signal even when a cycle time of synchronous CLKA is short (frequency is high) and the distance between a memory controller and a synchronous memory is physically long. SOLUTION: This unit is provided with a CLK phase adjusting section 101 generating a CLKB 102 of which a phase is more delayed than that of CLKA 208, and a signal latch section 100 synchronizing one part or all of signals outputted from a memory controller 202 and inputted to a SDRAM 206 with the CLKB 102. A memory controller 202 performs input/output of a signal in synchronism with the CLKA 208, a signal latch section 100 performs input/ output of a signal synchronizing with the CLKB 102, and a SDRAM 206 performs input/output of a signal in synchronism with the CLKA 208.</p> |
