| 摘要 |
PURPOSE: A low power memory core control device is provided, which reduces a power consumption during a control operation of a memory core, in a circuit design of semiconductor MML(Merged Memory Logic) field. CONSTITUTION: The memory core control device includes a memory cell block(105a), and sense amplifier blocks(104a,104c) which are located at each of an upper part and a lower part in correspondence to the above memory cell block and are connected to a pair of a bit line and a bit line bar of the memory cell block in turn. And a core control block is constituted in correspondence to the memory cell block, and controls the precharge of the bit line and the bit line bar by supplying an equal bit line precharge control signal(blp_d) to equalization blocks of the upper sense amplifier block and the lower sense amplifier block. The memory cell block and a memory cell block adjacent to the upper part or to the lower part of the memory cell block share the sense amplifier block located between them.
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