| 摘要 |
PURPOSE: A semiconductor memory device having a refresh function is provided to improve a refresh characteristic by controlling supply voltage of a sense amplifier driver according to states of a memory cell. CONSTITUTION: An input buffer and command decoder(31) receives an address and a command and generates an operating signal of a DRAM. A defect low address storage portion(41) stores low address information including a refresh defect according to a refresh command(REF) of the input buffer and command decoder(31). An internal address counter(36) generates addresses(IAX(0-i)) according to the refresh command(REF). An address comparator(42) compares addresses(SAX(0-i)) of the defect low address storage portion(41) with the addresses(IAX(0-i)) of the internal address counter(36). A row address latch(32) latches a row address according to the refresh command(REF) and a low active command(ACT). A column address latch(33) latches a column address according to a read/write command(RD/WT). A row pre-decoder(34) predecodes outputs(AX(0-i)) of the row address latch(32). A column pre-decoder(35) predecodes outputs(AY(0-i)) of the column address latch(33). A row decoder(38) selects a bit line according to an output of the row pre-decoder(34). A sense amplifier(39) is connected with bit lines of a memory cell array(40). The sense amplifier(39) is controlled by a sense amplifier controller(37). A row control circuit(43) supplies a sense amplifier enable signal(SAEN) to the sense amplifier controller(37) according to the row active command(ACT).
|
