发明名称 Architecture of psm-mpus and coprocessors
摘要 A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.
申请公布号 US2002087827(A1) 申请公布日期 2002.07.04
申请号 US20000751943 申请日期 2000.12.28
申请人 STARK GAVIN J.;WISHNEUSKY JOHN 发明人 STARK GAVIN J.;WISHNEUSKY JOHN
分类号 G06F9/50;(IPC1-7):G06F15/00 主分类号 G06F9/50
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