| 摘要 |
<p>The present invention provides a variable length decoder which can reduce the processing time. The variable length decoder of the present invention comprises plural decoding table address generation circuits, and a selector for selecting one of plural address candidates generated from these circuits. During decoding of one variable length code, the variable length decoder obtains address candidates for the next variable length code, and then selects one of the address candidates for the next variable length code on the basis of an obtained code length of the variable length code, to output the same to the decoding table RAM. &lt;IMAGE&gt;</p> |
