发明名称 Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction
摘要 A processor having a data providing unit comprises a first table for holding the address of a store instruction indexed by a data address at which data value is stored by the store instruction, a second table for holding the address of the store instruction indexed by a subsequent load instruction, a data storing unit for holding data indexed by the address of the store instruction, and a data providing controller. The data providing controller retrieves the load instruction and the store instruction, both instructions looking up a same data address from the first and second tables, and retrieves data which are employed by the store instruction corresponding to the load instruction from the data storing unit, based on the address of the load instruction, and provides the data for the processor as predictive data to which access by the load instruction is predicted.
申请公布号 US6415380(B1) 申请公布日期 2002.07.02
申请号 US19990237900 申请日期 1999.01.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SATO TOSHINORI
分类号 G06F9/38;(IPC1-7):G06F13/00 主分类号 G06F9/38
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