| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit reducing a test time of a memory while avoiding the use of a large relief analysis circuit.SOLUTION: A semiconductor integrated circuit 1 comprises a plurality of memories 11, a plurality of comparison circuits 12 for comparing an output value with an expectation value of each memory, a plurality of first registers 13 storing comparison result data of each comparison circuit, and a BIST (Built In Self Test) circuit 20 controlling the test of the plurality of memories and generating an expectation value. The BIST circuit includes a second register 23 for storing comparison result data transferred from the plurality of first registers, a relief data generator 24 for generating relief data which indicates the presence or absence of a defect in the memories and a defect position on the basis of the comparison result data stored in the second register, third registers 25, the number of which is smaller than that of the plurality of memories, for storing the relief data and a determination circuit 27 for outputting a relief disable signal when the total number of the relief data becomes larger than that of the third registers.SELECTED DRAWING: Figure 4 |
