| 摘要 |
The system comprises two memory devices within each memory cell for storage of a sample of analogue signal in one and of a sample of that signal substantially with opposite phase in the other, where the phase opposition is obtained by delaying the signal before applying to the other memory device. The matrix of analogue memory cells is laid out in a set of rows and columns, where each cell is linked to a writing bus and to a reading bus, and comprises two control inputs, and horizontal and vertical shift registers for applying the control signals to the cells for carrying out the operations of reading and writing. The writing bus and the reading bus (4,5) are connected to the input and output circuits (6,7), respectively, and analogously for the other device operating with the signal in phase opposition. The memory cell (3) comprises a storage capacitor (Cs) in floating connection between the writing bus (4) and a reference potential terminal (20) in a writing circuit with switches (S1,S2), and a reading circuit with switches (S3,S4) and a sense amplifier (21) connected to the reading bus (5). The control signals from the shift registers (8,9) are directed to the two inputs of an AND-gate (22), and the reading bus (5) is connected to an analogue-to-digital converter (12). The memory cell is implemented in the form of a differential cell, where the reference potential is common to the two memory devices. The two storage capacitors are linked by an optional switch in order to enlarge the pass-band of the cell. The system comprises a device for reconstituting the sampled signal by computing after digitization. |
