PRE-EMPHASIS SIGNAL GENERATOR CIRCUIT FOR HIGH-SPEED I/O DRIVER

摘要

PURPOSE: A pre-emphasis signal generator circuit for a high-speed I/O driver is provided to implement the principle of pre-emphasis more effectively and to eliminate the bottle neck state of speed. CONSTITUTION: In case that input data(DS) transit Low to High, the left input node of N1 becomes High directly. But the left node of N2 maintains an existing state during a delay time of 150-200p of the first delay unit. After the 150-200p delay, a DI node becomes a High signal. At the same time, as N2 is turned on and the Low signal of the left node of N2 is transmitted, P1 is turned on. As the result, an output node(emp) gets to a High state. After the second delay unit's 150-200p delay, an input High signal turns off P1 Tr through N2. At the same time with this, as N1 is turned on and N3 is turned on by the input High signal, the output node(emp) gets to a Low state.