SEMICONDUCTOR DEVICE HAVING SHALLOW TRENCH ISOLATION STRUCTURE AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A semiconductor device having a shallow trench isolation structure is provided to make defects in a cell region from penetrating into a shallow trench(STI) isolation layer by a thick buffering liner, by making the STI layer separating p-type field effect transistors have a thick sidewall oxide layer and by making the STI layer formed in the cell region have a relatively thick buffering liner. CONSTITUTION: A semiconductor substrate includes the cell region, a core region, a peripheral region and a plurality of trenches(106a,106b). Memory devices are formed in the cell region. The p-type field effect transistors and other circuit devices are formed in the core region and the peripheral region. The plurality of trenches separate the devices formed in the respective regions. The first sidewall oxide layer(108) is formed on the inside surface of the plurality of trenches. The second sidewall oxide layer(114) is formed on the first sidewall oxide layer of the trench formed in the core region and the peripheral region. The first buffering liner(110) is formed on the first sidewall oxide layer of the trench formed in the cell region and on the second sidewall oxide layer of the trench formed in the core region and the peripheral region. The second buffering liner(116) is formed on the first buffering liner of the trench formed in the cell region. Insulation materials are filled in the plurality of trenches.