| 摘要 |
PURPOSE: A method for fabricating a bit line lower plug of a semiconductor device is provided to prevent damage to a gate line in etching the bit line lower plug, by performing a chemical mechanical polishing(CMP) process on polysilicon deposited between gate lines and by growing selective silicon on the polysilicon. CONSTITUTION: A gate oxide layer, a polysilicon layer and a tungsten silicide layer are sequentially stacked on a semiconductor substrate(101) having a predetermined lower structure to form a pattern. A mask nitride layer(105) is stacked on the resultant structure, and a patterning etch process is performed to form the gate line(103). After a nitride layer(107), an interlayer dielectric and the first photoresist layer are sequentially stacked on the resultant structure to form a pattern, the pattern is dry-etched to the upper portion of the nitride layer by using the first photoresist layer as an etch barrier. The nitride layer is anisotropically etched to form a plug contact hole by using the first photoresist layer as an etch barrier. The first photoresist layer is removed. After polysilicon is deposited and filled in the contact hole, a CMP process is performed until the upper portion of the nitride layer is exposed. Selective silicon is grown on the polysilicon layer. An oxide layer(122) is deposited on the resultant structure and is mask-etched to form the bit line lower plug.
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