| 摘要 |
A frequency divider and method for dividing a clock signal. The frequency divider including a first configurable signal generator, a second configurable signal generator, a data source coupled to the signal generators providing configuration data based on instructions received at an instruction port, a sequencer generating the instructions coupled between the signal generators and the data source and passing the instructions to the instruction port of the data source, and combining logic coupled to the outputs of the signal generators to produce the reduced frequency signal. The method including generating a first signal having first and second counting intervals which are individually configurable and based on a rising edge of the clock signal, generating a second signal having third and fourth counting intervals which are individually configurable and based on a falling edge of the clock signal, and combining the signals to create the reduced frequency signal, wherein the output level of the reduced frequency signal changes after every counting interval.
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