发明名称 MOSFET with both elevated source-drain and metal gate and fabricating method
摘要 A method of forming a transistor and a semiconductor-metal-oxide transistor. The method at least includes provides a substrate; covers the substrate by a doped amorphous polysilicon layer and a barrier layer in sequence, and removes part of the barrier layer and part of the doped amorphous polysilicon layer to form a hole which expose part of the substrate; forms a dielectric layer on both the barrier layer and the hole, wherein the hole is not totally filled by the dielectric layer; forms a conductor layer on the dielectric layer, wherein the hole is not totally filled by both the conductor layer and the dielectric layer; forms a metal layer on the conductor layer; performs a planarizing process by using the barrier layer as a stop layer; and removing the barrier layer. The other at least includes a U-shaped dielectric layer which is located on a substrate; a U-shaped polysilicon layer which is located on the hollow of the U-shaped dielectric layer; a metal layer which is located on the hollow of the U-shaped polysilicon layer; a source doped region which is located in the substrate and is briefly located on one side of the U-shaped dielectric layer; a drain doped region which is located in the substrate and is briefly located on another side of the U-shaped dielectric layer; and an epi-like silicon layer which is located on both the source doped region and the drain doped region.
申请公布号 US2002066913(A1) 申请公布日期 2002.06.06
申请号 US20000729163 申请日期 2000.12.05
申请人 VANGUARD INTERNATIONAL SEMICONDUCTO CORPORATION 发明人 TSENG HORNG-HUEI
分类号 H01L21/336;(IPC1-7):H01L29/04;H01L31/036;H01L29/76 主分类号 H01L21/336
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