SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM

摘要

A data processing system in which high-speed data transfer rate low power consumption are both achieved by controlling both the working power supply voltage (VDDQ) of an external output buffer and the transistor size of the external output buffer through a control circuit (111) and selecting the lowest voltage for matching the impedance with that of a transmission line (100) so as to eliminate the need to terminate a bus with a resistor. Since the power consumption during data transfer is proportional to the square of the working power supply voltage, the power consumption can be reduced by lowering the working power supply voltage of the external output buffer. The apparent impedance increases as the working power supply voltage of the external output buffer is lowered, and the impedance can be decreased by increasing the transistor size of the external output buffer. A signal having no distortion in the waveform can be outputted by matching the output impedance (ON resistance) of the external output buffer with the impedance of the transmission line.