| 发明名称 |
THREE-DIMENSIONAL MEMORY ARRAY AND METHOD OF FABRICATION |
| 摘要 |
A multi-level memory array is described employing rail-stacks. The rail-stacks include conductor (40) and semiconductor layers (38, 39 and 41). The layers are generally separated by an insulating layer used to form antifuses (42). In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack. Methods for fabricating a multi-level memory array are also provided. |
| 申请公布号 |
WO0184553(A3) |
申请公布日期 |
2002.06.06 |
| 申请号 |
WO2001US13575 |
申请日期 |
2001.04.25 |
| 申请人 |
MATRIX SEMICONDUCTOR, INC.;KNALL, N., JOHAN;JOHNSON, MARK |
发明人 |
KNALL, N., JOHAN;JOHNSON, MARK |
| 分类号 |
G11C16/04;H01L21/77;H01L21/8246;H01L21/84;H01L27/06;H01L27/102;H01L27/115 |
主分类号 |
G11C16/04 |
| 代理机构 |
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代理人 |
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