| 摘要 |
PURPOSE: A time clock phase compensator in a CDMA base station is provided to reduce a load of a processor by compensating for a phase of 2 second clock in a hardware method. CONSTITUTION: A GPS receiving board(100) receives a system clock and a time clock from a GPS satellite. A phase locked loop(200) synchronizes a phase of a system clock received by the GPS receiving board(100). A voltage controlled oscillator(300) generates an oscillating frequency in response to the system clock from the phase locked loop(200). An offset controller(400) divides an oscillating frequency from the voltage controlled oscillator(300). The offset controller(400) detects whether an offset is generated in the divided oscillating frequency. When the offset is generated in the divided oscillating frequency, the offset controller(400) controls the offset according to an offset control signal.
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