Integrated passive devices with reduced parasitic substrate capacitance

摘要

A passive electrical component structure comprises a semiconductor body (20) with a sealed air gap (26) formed in the semiconductor body (20) underlying a patterned metal layer (46). A method of forming high quality inductors and capacitors in semiconductor integrated circuits utilizes one or more sealed air gaps (26) in a supporting substrate under the passive devices. The process is compatible with standard silicon processing and can be implemented with high temperature processing at the beginning, middle, or end of an integrated circuit fabrication process. A one micron air-gap in a high resistivity epitaxial layer results in a parasitic capacitance equivalent to 3.9 micron thick silicon oxide or a 11 micron thick depletion layer in silicon.