发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To overcome the problem of the conventional analog PLL such that has a narrow lock range and the conventional digital PLL that has a deteriorat ed phase noise characteristic. SOLUTION: The PLL circuit provided with an analog phase comparator 1, a low pass filter 2 and a voltage controlled oscillation circuit 3, is provided with a digital phase comparator 4 and an analog switch 5, the switch 5 is connected to the digital phase comparator 4 when the voltage controlled oscillation circuit 3 is unlocked, and an output from the phase comparator 4 is given to the low pass filter 2, and the switch 5 is switched to the position of the analog phase comparator 1 when the voltage controlled oscillation circuit 3 is locked, and an output from the phase comparator 1 is given to the low pass filter 2.
申请公布号 JP2002152039(A) 申请公布日期 2002.05.24
申请号 JP20000340271 申请日期 2000.11.08
申请人 MIHARU COMMUNICATIONS CO LTD 发明人 MORI SHIGETAKA
分类号 H03L7/087 主分类号 H03L7/087
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