| 摘要 |
Described is a level-detection circuit having hysteresis and which may be powered down without losing the last state of the circuit. The level-detection circuit includes a first detection circuit, a trip-level adjustment circuit, and a second detection circuit. The first detection circuit may be essentially an inverter, with the output signal of the inverter fed to an input of the second detection circuit. The trip-level adjustment circuit is connected to the output signal and has control connections tied to the input signal. The trip-level adjustment circuit also includes control connections tied to the output signal of the circuit. In short, the trip-level adjustment circuit is configured such that one element of the trip-level adjustment circuit is connected in parallel with one element of the inverter of the first detection circuit when the input signal moves from a one potential to another potential. In addition, the trip-level adjustment circuit may include another element connected in parallel with another element of the inverter of the first detection circuit when the input signal moves in the opposite direction, e.g. from the other potential to the one potential. Moreover, the circuit includes latching circuitry, under control of an enable signal, configured to latch a last state of the trip-level adjustment circuit during a power-down event so that the input signal to the second detection circuit will have the same state when the circuit is powered back up.
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