发明名称 ACCUMULATING ADDITION-SUBTRACTION CIRCUIT FOR ABSOLUTE VALUE
摘要 PROBLEM TO BE SOLVED: To provide an accumulating addition-subtraction circuit for the absolute value capable of executing accumulating addition-subtraction for the absolute value at a high speed on a small scale circuit. SOLUTION: The accumulating addition-subtraction circuit for the absolute value is provided with an adder-subtracter performing addition-subtraction of two data that are expressed by a complement of 2, a control unit of an adder-subtracter generating a control signal that controls selection whether aforementioned two data are to be added or subtracted and outputting to the adder-subtracter, and a register housing calculated result of the adder-subtracter and also supplying to the adder-subtracter.
申请公布号 JP2002132494(A) 申请公布日期 2002.05.10
申请号 JP20000327715 申请日期 2000.10.26
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 SHOJI TAKEMASA;MASUDA KOICHI
分类号 G06F7/505;G06F7/50;(IPC1-7):G06F7/50 主分类号 G06F7/505
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