COLUMN ADDRESS DECODER FOR CONTROLLING COLUMN SELECTION LINE ENABLE TIME POINT, DECODING METHOD OF THE SAME, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

摘要

PURPOSE: A column address decoder for controlling a column selection line enable time point, a decoding method of the same, and a semiconductor device having the same are provided to enable stably a column selection line regardless of a length of a data line. CONSTITUTION: A plurality of inverters(800,805) is used for inverting column addresses(CAi,CAj) and outputting inverted column addresses(CAiB,CAjB). An inverter(810) is used for inverting a CSL enable signal(PCSLEP). The first to the fourth decoding portions(820-850) are used for latching a logically combined value of the column addresses(CAi,CAj) and the inverted column addresses(CAiB,CAjB) in response to a CSL enable signal and generating pre-decoded column addresses(DCAij,DCAijB,DCAiBj,DCAiBjB) by combining logically the latched signal and the CSL enable signal(PCSLEP).