| 摘要 |
After a provisional layout in a sub-module of a semiconductor integrated circuit is performed, a path optimizing inter-sub-modules process is executed, and the layout and wiring among sub-modules are performed. If any part of the wiring among sub-modules does not satisfy a specified delay restriction, a provisional-layout correction process is executed to correct the provisional layout of cells in a sub-module. These processes are repeated, and then an entire layout of cells is determined.
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