发明名称 |
Data processing system with an enhanced cache memory control |
摘要 |
A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.
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申请公布号 |
US6381680(B1) |
申请公布日期 |
2002.04.30 |
申请号 |
US19980087900 |
申请日期 |
1998.06.01 |
申请人 |
HITACHI, LTD.;HITACHI MICRO COMPUTER ENGINEERING, LTD. |
发明人 |
NISHIMUKAI TADAHIKO;HASEGAWA ATSUSHI;MATSUMURA MASARU |
分类号 |
G06F12/08;(IPC1-7):G06F12/00;G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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