| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an FIFO memory control circuit which can protect the writing and reading control of an FIFO memory from being transferred or put into incorrect operation sequence by incorrect data inputted by the influence of a transient state of a device start-up, noises, etc. SOLUTION: A WENB generating unit 3 generates a WENB signal and practices the write control of an FIFO memory unit 1. If an SOC-IN signal is detected once, even if the next SOC-IN signal is detected before 53 counts, '0' is not loaded on a counter. The WENB generating unit 3 also controls an SOC mask unit 6 so as not to write an incorrect SOC signal in the FIFO memory unit 1. This control is practiced during a period from the detection of the SOC-IN signal till the count reaches 53 by masking the inputted SOC-IN signal so as to have a level 'L' by the SOC mask unit 6.</p> |
