| 摘要 |
PURPOSE: A voltage level detecting circuit and a voltage generating circuit using the same is provided to stabilize a fed-back voltage level although a voltage detection level is varied according to process variation, and to improve an operating speed by reducing a variation width of the fed-back voltage. CONSTITUTION: A PMOS transistor(M5) and an NMOS transistor(N11) are connected in series between an internal power supply voltage(VINT) and a node(F), and have their gates connected to receive a high voltage(VPP) respectively. An NMOS transistor(N12) is connected between the node(F) and a ground voltage, and has a gate connected to receive a voltage(Vout1). A differential amplifier(AMP1) amplifies a difference between a reference voltage(Vref) and a voltage of the node(F), and generates the voltage(Vout1). An inverter(I13) receives the voltage(Vout1) to generate a high voltage detection signal(VPPS).
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