| 摘要 |
<p>The digital phase locked loop digitises a baseband video signal (S1) from a source (12) using an A/D converter (20), which feeds a video processing and display unit (14). A clock signal (S5), of four times colour subcarrier frequency, is generated by a voltage controlled oscillator (26) and is fed to the converter (20). The timing unit (24) is synchronised by a feed of the clock signal and by deflection timing signals from the display unit (14), enabling production of synchronising signals (HS,VS,BG). The burst accumulator may now produce burst vector coordinates (X,Y) for the digitised video signal (S2), which are translated to polar form by the converter (30). Further processing by the frequency error detector (42) and the lock detector (44) enables the limiter (50) to provide a limiting condition signal (S15) to the jitter processor (40), and both limiting phase angle sign and magnitude signals (S11,S12). The jitter processor produces noise indicating signal bits (B0,B1) to the picture enhancement processor (18).</p> |
