发明名称 Patterning method in semiconductor device fabricating process
摘要 In a semiconductor device fabricating process, a chemical amplification resist layer is formed on an insulating film formed on a semiconductor substrate, and the chemical amplification resist layer is patterned to form an opening. The insulating film formed on the semiconductor substrate is wet-etched using the patterned chemical amplification resist layer as a mask. Before the wet-etching is carried out, a surface treatment is conducted for the patterned chemical amplification resist layer to form an insoluble layer at a surface of the patterned chemical amplification resist layer, thereby to elevate a wet-etching-resistance of the patterned chemical amplification resist layer. Thus, deformation of a resist pattern formed of the patterned chemical amplification resist layer is prevented in the wet etching process, so that an opening pattern of a desired shape is formed in the insulating film.
申请公布号 US6376155(B2) 申请公布日期 2002.04.23
申请号 US19990317855 申请日期 1999.05.25
申请人 NEC CORPORATION 发明人 ITO KATSUYUKI
分类号 G03F7/38;G03F7/11;G03F7/40;H01L21/027;H01L21/033;H01L21/306;H01L21/311;(IPC1-7):G03F7/26;H01L21/27 主分类号 G03F7/38
代理机构 代理人
主权项
地址