发明名称 Memory control apparatus and its control method
摘要 <p>A memory control apparatus (3) according to the invention is interposed between a central processing unit (1) and a memory device (2) to store data and has: a channel control unit (35) to control a data transfer to/from the central processing unit (1); a drive control unit (36) to control a data transfer to/from the memory device (2); a plurality of cache memories (33, 34) to temporarily store the data which is transferred between the central processing unit (1) and the memory device (2); and a cache memory control unit (37) having selecting means for selecting the cache memory to store the data which is transferred from the memory device (2). The memory control apparatus (3) selects the cache memory to store the data so as to almost equalize use amounts in the plurality of cache memories, thereby controlling the allocation of the cache memories and enabling a cache memory space to be effectively used.</p>
申请公布号 EP1193600(A2) 申请公布日期 2002.04.03
申请号 EP20010126232 申请日期 1996.02.16
申请人 HITACHI, LTD. 发明人 TAMURA, MISAKO;ASAKA, YOSHIHIRO;KISHIRO, SHIGERU;YAMAMOTO, AKIRA
分类号 G06F3/06;G06F11/10;G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F3/06
代理机构 代理人
主权项
地址