发明名称 INTEGRATED MEMORY
摘要 PROBLEM TO BE SOLVED: To properly read and write a data signal from/in remaining memory cells when a defective memory cell causing a short circuit exists across a row line and a column line, in an integrated memory provided with memory cells having a magnetic resistance memory effect. SOLUTION: Column lines BL0-BLn are connected with a read amplifier 3, and to read a data signal DA from a selected memory cell MC3 via the column line BL2 connected with the selected memory cell MC3, or to write the data signal DA in the sel.ected memory cell MC3, row lines WL0-WLm can be connected to a selection signal terminal GND. In that case, one or plural column lines BL0, BL1, BLn which are not connected with the memory cell MC3 are controlled so as to be electrically insulated in a sense amplifier when reading or writing the data signal DA.
申请公布号 JP2002093189(A) 申请公布日期 2002.03.29
申请号 JP20010201076 申请日期 2001.07.02
申请人 INFINEON TECHNOLOGIES AG 发明人 POECHMUELLER PETER
分类号 G11C11/14;G11C11/15;G11C29/04;H01L21/8246;H01L27/105;(IPC1-7):G11C29/00 主分类号 G11C11/14
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