发明名称 SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT
摘要 PURPOSE: To provide a semiconductor memory integrated circuit which can perform an efficient test using a memory tester. CONSTITUTION: In a semiconductor memory integrated circuit provided with a shift register 4 which converts parallel data which is controlled by a clock and read out to a main data line from a memory cell array into serial data, and converts write-in data supplied from a data input/output buffer in serial into parallel data, a combination of numbers (n) of data input/output terminals DQn allotted to the main data line MDQ is rearranged on the data input/output terminals DQn by intersecting one part of the main data lines MDQ between the memory cell array and a shift register.
申请公布号 KR20020022602(A) 申请公布日期 2002.03.27
申请号 KR20010057932 申请日期 2001.09.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HARA TAKAHIKO;KOYANAGI MASARU;NAGAI TAKESHI
分类号 G01R31/28;G11C11/401;G11C11/409;G11C11/4096;G11C29/00;G11C29/12;G11C29/38;H01L21/822;H01L21/8242;H01L27/04;H01L27/108;(IPC1-7):G11C11/409 主分类号 G01R31/28
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