METHOD FOR FABRICATING INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING GATE LINE AND BIT LINE FROM BEING SHORT-CIRCUITED

摘要

PURPOSE: A method for fabricating an integrated circuit semiconductor device is provided to prevent a gate line and a bit line from being short-circuited, by preventing the gate line from being opened in forming a bit line contact hole. CONSTITUTION: A plurality of gate lines(49) are formed on a silicon wafer(41). A plurality of pads(53) are formed on the silicon wafer among the gate lines. An interlayer dielectric is formed on the entire surface of the silicon wafer having the gate lines and pads wherein the interlayer dielectric is thick in the center(C) of the silicon wafer and is thin in the edge(E) of the silicon wafer. The interlayer dielectric(55) is planarized in a condition that the etch rate of the interlayer dielectric in the edge of the wafer is fast and the etch rate of the interlayer dielectric in the center of the wafer is slow. The planarized interlayer dielectric is selectively etched by a photolithography process to form the bit line contact hole(57) opening the pad while not exposing the gate line to the center and edge of the silicon wafer. The bit line(59) is formed in the bit line contact hole.