| 摘要 |
PROBLEM TO BE SOLVED: To provide an automatic routing design method, an automatic routing design apparatus, and a storage medium where an automatic routing avoiding the occurrence of a parasitic MOS is enabled and the shortening of TAT is enabled in a routing design of an analog circuit portion. SOLUTION: On the basis of a wiring condition data file D7 and a MOS induction node data file D4, if it is not a parasitic MOS induction node (S12: 'NO'), it is wired by an usual automatic routing processing (S20), and if it is the parasitic MOS induction node(S12: 'YES'), after it is temporarily wired in the target point direction (S13), if it is passed through a wiring inhibition area F (S14: 'YES'), an alternative route is set by bending it before passing in the target point direction (S15), and if it is not passed through the wiring inhibition area F (S14: 'NO') but it is intersected with a pair of portion sides (S16: 'YES'), it is set so as to be in parallel with the pair of portion sides by bending it in the target point direction (S17) after it is intersected with one of a pair of portion sides.
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