发明名称 |
Integrated circuit memory devices having circuits therein that preserve minimum /RAS TO /CAS Delays |
摘要 |
A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.
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申请公布号 |
US6356489(B2) |
申请公布日期 |
2002.03.12 |
申请号 |
US20010766358 |
申请日期 |
2001.01.19 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE SANG-BO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C8/06;G11C11/409;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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