| 摘要 |
<p>A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each, tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data is loaded into various lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache, such as a task ID. A miss counter (532) counts each miss and a monitoring task (1311) determines a miss rate for memory requests. If a selected miss rate threshold value is exceeded, the digital system is reconfigured in order to reduce the miss rate. The cache is reconfigured in response to an operation command (1314), such that each tag in the array of tags that contains a specified qualifier value is modified in accordance with the operation command. Other types of reconfiguration can be performed, such as remapping a selected program portion to operate in a different address range, locking a portion of the data entries within the cache, or defining addresses corresponding to a selected program task as uncacheable, for example. <IMAGE></p> |
