发明名称 MEMORY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a memory circuit which can perform read-out even when 2n+1 is the maximum address of a memory in combination of 2n+1 and 2n+2, in a memory which is divided into an even numbered address block 201 and an odd numbered address block 202 and which can read out continuous two words in parallel. SOLUTION: This device is provided with a register 209 storing data of the maximum address +1 of a memory and an output selector 210 selecting either of output of the even numbered address block 201 or output of the register 209.</p>
申请公布号 JP2002056685(A) 申请公布日期 2002.02.22
申请号 JP20000237079 申请日期 2000.08.04
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ASAHI RYUICHI;TANAKA HISAYOSHI
分类号 G11C11/41;G11C11/401;G11C16/02;(IPC1-7):G11C16/02 主分类号 G11C11/41
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