| 摘要 |
<p>A circuit and method for stress testing a transistor (110) in an integrated circuit device comprising: an external connection pad (GST) coupled to the transistor; a first switch (Sn) coupled between the transistor and circuitry (130) within the integrated circuit device to which the transistor is connected during normal operation of the device; a second switch (Sg) coupled between the transistor and test circuitry for testing the transistor; and detecting means (C1, C2, DZ1, DZ2, DZ3) coupled to the pad for detecting when a signal applied thereto has at least a predetermined slew rate, and for disabling the first switch and enabling the first switch in response to this detection. The test is unaffected by the normally-operating circuitry; the test does not require an extra pad per gate for testing purposes; and the test may be performed during the stress state of the power transistor, allowing detection of small defects. <IMAGE></p> |
