| 摘要 |
An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve. The level shifting circuit includes a reference transistor, whose current density matches that of the reset transistors inside the cells, which shifts the potential at the DAC's output upward by an amount equal to the reference transistor's threshold voltage (which matches the threshold voltage of each reset transistor of the cell array or a row of the cell array) to produce the XDR reset potential. To cause the control bits asserted to the DAC to establish breakpoints which in turn cause the analog-to-digital converter (ADC) of the image sensor array to assert (predictably) an expected set of digital output bits in response to each read of a cell exposed to light of known intensity, both the ADC and the DAC operate at the same reference voltage, and the level shifting circuit's reference transistor's biasing matches that of the reset transistors inside the cells.
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