| 摘要 |
PROBLEM TO BE SOLVED: To overcome the problem such that, when low source potential occurs during high speed operation of a system clock, the semiconductor integrated circuit runs away due to the low reset level. SOLUTION: This device is so constituted that it has a power source 1 whose voltage is increased, a ladder resistor 3 which has a first divided potential point 3X of a first divided potential V1, a second divided potential point 3Y of a second divided potential V1, and a third divided potential point 3Z of a third divided potential V3, that it has a first potential comparator circuit 5X which outputs a reset release signal when V1 exceeds a reference potential Vr, and outputs a reset signal when V1 falls less than the reference potential Vr, a voltage step-up status detector which changes a signal C from 'L' to 'H' when a voltage step-up occurs and reset is released and V2 exceeds Vr, and changes the signal C from 'H' to 'L' when the first potential comparator circuit 5X outputs a reset signal of 'L', and a switching circuit which connects the first divided potential point 3X and the first potential comparator circuit 5X on receiving the signal C of 'L' and 'H' output from a NOT circuit 9, and connects the third divided potential point 3Z and the first potential comparator circuit 5X on receiving the signal C of 'H' and 'L' output from the NOT circuit 9.
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