| 摘要 |
PROBLEM TO BE SOLVED: To enhance maximum effective power gain by increasing the shut-off frequency without shortening the gate length. SOLUTION: The junction gate field effect transistor comprises n-type source impurity region 3 and drain impurity region 4 connected with the opposite sides of an n-type channel forming impurity region 2, and p-type gate impurity region 6 and gate electrode 9 formed in the surface side region in the channel forming impurity region 2. The gate impurity region 6 and/or the channel forming impurity region 2 has an impurity density difference in the channel direction. The density difference is high on the source side and low on the drain side. The gate impurity region 6 (impurity region 2) has such a concentration profile as not varying the gate capacity (effective impurity concentration of channel and channel resistance) for a conventional FET having an impurity concentration optimized by a constant value.
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