| 发明名称 |
Buffer memory has multiplexing to latches improves stability without extra latches |
| 摘要 |
A buffer memory (2) has several Latch stages (L1-Ln-1) with multiplexer switch (7) connected to the latch (6) back coupling loop.
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| 申请公布号 |
DE10035424(A1) |
申请公布日期 |
2002.01.31 |
| 申请号 |
DE2000135424 |
申请日期 |
2000.07.20 |
| 申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
NYGREN, AARON |
| 分类号 |
H03K5/13;H03K5/135;H04L25/05;(IPC1-7):H04L12/54;G06F5/06 |
主分类号 |
H03K5/13 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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